Available DSP IP Cores from DSPIA Inc.

• High Speed RS (Reed-Solomon) Encoder/Decoder
  • Smaller than most decoders
  • Optimized for FPGA and ASIC implementations
• CORDIC
  • Rectangular to Polar Conversion
  • Polar To Rectangular Conversion
  • ATAN implementation
  • Speed vs. Latency Configuration
• FFT, IFFT cores
  •  suitable for DMT & OFDM
  • 32 to 256 Point Real or Complex Inputs
  • Bit Reversed or Linear Input
  • Bit Reversed or Linear Output
  • internal Radix-4 or Radix-8 Butterfly
• DDS (Direct Digital Frequency Synthesis or DDFS) for NCO applications.
  • Output Bit Width Parameterized.
  • Very High Speed
  • Speed vs. Latency Optimization
• 32 Bit RISC Core with SIMD and DSP Instructions
  • Instructions subset of popular MIPS architecture
  • Configurable SIMD Instructions
  • Configurable DSP Instructions
• Multiplier for Montgomery Modular Multiplication & Exponentiation
  • High Speed implementation
  • Low Power and Low Area
  • Configurable for Input Size

All of these cores are parameterized and can be fully customized per licensee's requirements.

All Cores are available in FPGA netlist format or in Verilog RTL format for ASIC synthesis.

Please contact kal@dspia.com for more information and pricing.

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